--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   18:15:30 10/31/2012
-- Design Name:   
-- Module Name:   C:/Users/my123wing/Documents/Xilinx_Project/CG3207/8051_clone/nus-3207-team38/8051_s1-s6_NewCode/Testing_Timer_Handler.vhd
-- Project Name:  Merging_NONE_Interrupt
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Tmer_Handler
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY Testing_Timer_Handler IS
END Testing_Timer_Handler;
 
ARCHITECTURE behavior OF Testing_Timer_Handler IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Timer_Handler
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         TMOD_reg : IN  std_logic_vector(7 downto 0);
         TCON_reg : IN  std_logic_vector(7 downto 0);
         TH0_reg : IN  std_logic_vector(7 downto 0);
         TL0_reg : IN  std_logic_vector(7 downto 0);
         TH1_reg : IN  std_logic_vector(7 downto 0);
         TL1_reg : IN  std_logic_vector(7 downto 0);
         T1 : IN  std_logic;
         T0 : IN  std_logic;
         INT1 : IN  std_logic;
         INT0 : IN  std_logic;
         Timer_Changed : OUT  std_logic;
         ack_changed : IN  std_logic;
         OUT_TH0_reg : OUT  std_logic_vector(7 downto 0);
         OUT_TL0_reg : OUT  std_logic_vector(7 downto 0);
         OUT_TH1_reg : OUT  std_logic_vector(7 downto 0);
         OUT_TL1_reg : OUT  std_logic_vector(7 downto 0);
         OUT_TCON_reg : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal TMOD_reg : std_logic_vector(7 downto 0) := (others => '0');
   signal TCON_reg : std_logic_vector(7 downto 0) := (others => '0');
   signal TH0_reg : std_logic_vector(7 downto 0) := (others => '0');
   signal TL0_reg : std_logic_vector(7 downto 0) := (others => '0');
   signal TH1_reg : std_logic_vector(7 downto 0) := (others => '0');
   signal TL1_reg : std_logic_vector(7 downto 0) := (others => '0');
   signal T1 : std_logic := '0';
   signal T0 : std_logic := '0';
   signal INT1 : std_logic := '0';
   signal INT0 : std_logic := '0';
   signal ack_changed : std_logic := '0';

 	--Outputs
   signal Timer_Changed : std_logic;
   signal OUT_TH0_reg : std_logic_vector(7 downto 0);
   signal OUT_TL0_reg : std_logic_vector(7 downto 0);
   signal OUT_TH1_reg : std_logic_vector(7 downto 0);
   signal OUT_TL1_reg : std_logic_vector(7 downto 0);
   signal OUT_TCON_reg : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Timer_Handler PORT MAP (
          clk => clk,
          rst => rst,
          TMOD_reg => TMOD_reg,
          TCON_reg => TCON_reg,
          TH0_reg => TH0_reg,
          TL0_reg => TL0_reg,
          TH1_reg => TH1_reg,
          TL1_reg => TL1_reg,
          T1 => T1,
          T0 => T0,
          INT1 => INT1,
          INT0 => INT0,
          Timer_Changed => Timer_Changed,
          ack_changed => ack_changed,
          OUT_TH0_reg => OUT_TH0_reg,
          OUT_TL0_reg => OUT_TL0_reg,
          OUT_TH1_reg => OUT_TH1_reg,
          OUT_TL1_reg => OUT_TL1_reg,
          OUT_TCON_reg => OUT_TCON_reg
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
	variable infinite: STD_LOGIC;
   begin		
      -- hold reset state for 100 ns.
		rst<='1';
      wait for 100 ns;	
		rst<='0';
		
		wait for 100 ns;
		TCON_reg <= "01010000";
		TMOD_reg <= "00000011";
		TH1_reg <= "11110000";
		TL1_reg <= "11111111";
		TH0_reg <= "11111100";
		TL0_reg <= "11111111";
		T1 <= '0';
		T0 <= '0';
		INT1 <= '0';
		INT0 <= '0';
		ack_changed <= '0';
      -- insert stimulus here 
		
		wait for clk_period * 24;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		
		wait for clk_period * 12;
		if( Timer_Changed = '1' ) then
				ack_changed <= not ack_changed;
				TH0_reg <= OUT_TH0_reg;
				TL0_reg <= OUT_TL0_reg;
				TH1_reg <= OUT_TH1_reg;
				TL1_reg <= OUT_TL1_reg;
				--TCON_reg <= OUT_TCON_reg;
		end if;
		wait;
   end process;
	
--	process(Timer_Changed)
--	begin
--			if( Timer_Changed = '1' ) then
--				ack_changed <= not ack_changed;
--				TH0_reg <= OUT_TH0_reg;
--				TL0_reg <= OUT_TL0_reg;
--				TH1_reg <= OUT_TH1_reg;
--				TL1_reg <= OUT_TL1_reg;
--				--TCON_reg <= OUT_TCON_reg;
--			end if;
--	end process;
END;
